1. Field of the Invention
Generally, the present disclosure relates to integrated circuits, and, more particularly, to the use of design-for-test elements for resetting core logic to a known state.
2. Description of the Related Art
Design-for-Testability (DFT) is a technique that enhances a microcircuit's testability by incorporating certain features into the microcircuit's design to facilitate testing of the manufactured product. The goal of such a design is to make difficult-to-test sequential circuits easier to test by replacing traditional sequential elements, such as flip flops (hereinafter called flops) with scannable sequential elements, called scan cells, and then connecting the scan cells together to form scan chains. A scan cell is a normal latch or flip-flop with an additional input, called the scan input, and an additional output, called the scan output. The scan output of one scan cell connects to the scan input of the next scan cell to form a scan chain. You can then shift data serially into and out of the scannable elements to inject test patterns into, or receive test results from, a manufactured chip during testing. The injected data appears at the outputs of the microcircuit's scannable sequential elements during operation.
Typically, each scannable sequential element is part of the functional core logic of the microcircuit's design, and each may need to be reset during reset conditions, such as a power-on reset condition. In a traditional microcircuit design, each scannable flop contains set or reset logic that is connected to a reset tree for setting the flop to a known state upon the reset condition. However, microcircuits may contain large numbers of such flops, resulting in reset trees and per-flop reset logic that require large amounts of area. Furthermore, because reset trees typically operate at full functional clock speeds, they also consume additional power and present timing challenges.